The present disclosure relates to the fabrication of field-effect transistors in an integrated circuit, and more particularly, relates to methods for modifying mechanical stresses induced upon the transistors' gate channel during the fabrication of transistors which feature the use of sidewall spacers on the transistor gate structures.
Very large scale integrated (VLSI) circuits using field effect transistors (FET) experience problems with the trapping of hot or energetic electrons to affect the lateral electrical field strength and carrier mobility in the transistor gate regions, particularly in the regions adjacent to the device source and drain. As transistor geometric sizing and distances scale down, carrier mobility and channel hot electrons within the FET devices begin to experience greater levels of instability. Many factors can influence this carrier mobility and electron stability. These factors (including substrate structure, substrate doping, source/drain dopant junctions) and gate channel dimensions can be adjustable to some extent during the fabrication of these circuits.
FIG. 1 illustrates a cross-sectional view of a field-effect transistor 100 featuring the use of sidewall spacer films to allow adjustments of the transistors' source/drain dopant junctions. The transistor's gate region comprising of the gate electrode 102, gate sidewall liners 103, and gate oxide 104 is formed on top of a substrate 105. The gate sidewall liners 103 are situated along the side walls of the gate electrode and extends outward to some length from the gate electrode. As shown, the transistor 100 is built upon the semiconductor substrate 105 with isolation structures 106a and 106b formed to provide electrical isolation between transistors. The area in the substrate 105 under the gate region is the transistor's gate channel. Sidewall spacers 108a and 108b are situated adjacent to the sidewall liners such that the sidewall liners are located directly between the spacers and gate region with the top of the spacers sloping down from the top of the gate sidewall liner to the outer edge of the sidewall liner extension that extends along the substrate from the gate electrode.
Although the spacers 108a and 108b offers much improvement for FET control and stability, there is a negative aspect to their use. The stress from the spacers combined with the stress from films subsequently formed on top of the transistor induced upon the gate region will affect the carrier and electron mobility along the gate channel. FIG. 2 illustrates the relationship between the transistor drain current (Id) flow versus stress applied onto the transistor gate channel region for an n-channel metal-oxide-silicon (NMOS) field-effect transistor. Specifically, for NMOS field-effect transistors, drive current improves with reduced stress in the gate channel. Stress affects upon transistor performance, usually accounted for during characterizations of the fabrication processes, have become a larger and more difficult issue as transistor geometric sizing and distances continue to scale down. It has become increasingly more desirable to address the controllability of and levels of stress induced by the spacer layer and subsequent layers on top of the gate region.
What is needed is an improved device with reduced channel stress when the spacers are used.